Data processing using resistive memory arrays

ABSTRACT

In an example, a method includes receiving, in a memory, input data to be processed in a first and a second processing layer. A processing operation of the second layer may be carried out on an output of a processing operation of the first processing layer. The method may further include assigning the input data to be processed according to at least one processing operation of the first layer, which may comprise using a resistive memory array, and buffering output data. It may be determined whether the buffered output data exceeds a threshold data amount to carry out at least one processing operation of the second layer and when it is determined that the buffered output data exceeds the threshold data amount, at least a portion of the buffered output data may be assigned to be processed according to a processing operation of the second layer.

BACKGROUND

Resistive memory devices, such as ‘memristors’, have been described inwhich an electrical component is capable of being written with aresistance in a non-volatile manner. Use of arrays of such devices hasbeen proposed for carrying out logical operations, for example in thecontext of ‘deep learning’ applications.

In some computing applications, for example deep learning applications,a logical operation is carried out on input data to provide an output ina first layer of processing. Logical operations are then carried out onthe output in a subsequent layer of processing, in some examples for aplurality of iterations. Such a processing scheme has been proposed foruse in fields such as big data analysis, image and speech recognition,machine learning and other computationally complex tasks.

BRIEF DESCRIPTION OF DRAWINGS

Non-limiting examples will now be described with reference to theaccompanying drawings, in which:

FIG. 1 shows an example method of processing in multiple processinglayers;

FIG. 2 shows an example method of allocating processing resources;

FIGS. 3a-c are simplified schematics of a section of an example memory;

FIG. 4 is a simplified schematic of an example processing apparatus;

FIG. 5 is a simplified schematic of an example processing unit of aprocessing apparatus;

FIGS. 6 and 7 show example methods of allocating processing resources;and

FIG. 8 is a schematic representation of an example of a data packet.

DETAILED DESCRIPTION

FIG. 1 is an example of a method, which may be a computer implementedmethod, of carrying out processing in at least one layer of a multilayerprocessing task. In block 102, input data is received in a memory, whichmay for example be a data buffer and may be provided by dynamic randomaccess memory (DRAM). In some examples, the memory may comprisesembedded DRAM (eDRAM), which is provided on a chip or die on whichprocessing apparatus to process the data is also provided. In otherexamples, other forms of memory (which may be embedded memory) may beprovided.

The input data is to be processed in at least a first and a secondprocessing layer, wherein the processing layers are to be applied to thedata such that in the second processing layer a processing operation iscarried out on output data of a processing operation of the firstprocessing layer. In some examples, there may be more processing layers,for example on the order to 10, 20 or 30 processing layers, with eachprocessing layer operating on an output of a preceding layer.

For example, a first layer of processing may operate on a stream ofinput data (sometimes termed channels), which may be any data, such asspeech, hand writing, images, experimental data, etc. In each layer, anumber of input channels may processed to form a number of outputchannels. The output channels may form the input channels of a furtherlayer.

In some examples, for example from ‘deep learning’ processingtechniques, data may be subjected to processing operations in one orseveral processing layers termed ‘convolution’ layers, in which an inputchannel is convolved with a pre-defined n_(x)n kernel (which may be amatrix operand) to generate an output channel. Other layers may compriseat least one pooling layer, at least one transformation layer, and atleast one classification layer. In a pooling layer, an input channel isdown-sized by a pooling function (for example, providing a maximum,minimum, average, or the like) to produce an output. In a transformationlayer, an input channel (which may be the output of a pooling layer) maybe transformed to using a non-linear function such as tan h(x) (which isan example of a sigmoid function). This may form the input to aclassification layer, in which the input may be convolved with apre-defined 1×1 kernel. This layer may generate an output of theapplication.

Of these, the convolution process, which may be a multilayer process,may be the most computationally intensive and may account for around, orabove, 80% of the computational resources. Therefore, in the examplesbelow, a processing pipeline may be designed to accelerate processing ofat least some convolution processing.

Block 104 comprises assigning the input data to be processed accordingto at least one processing operation of the first processing layer usingat least one resistive memory array. In an example, a resistive memoryarray may comprise a two-dimensional grid of resistive memory elements,which may be a crossbar array. Such an array may be written by settingthe resistive value of at least one resistive memory element. In someexamples, the elements may be binary having one of two values forexample, representing 0 or 1. However, resistive memory elements whichcan take a plurality of values, for example 32 distinct levels (whichcan represent 5 bits), have been demonstrated. A crossbar array ofmemristors or other resistive memory elements can process an inputvoltage vector to provide an output vector in which the input values areweighted by the conductance at each element of the array. Thiseffectively means that the array performs a ‘dot product’ matrixoperation on the input to produce an output (and thus such arrays havesometimes been termed ‘dot product engines’). The weights of theelements can be ‘programmed’ by subjecting the elements to voltagepulses, each voltage pulse incrementally changing the resistance of thatelement. Such arrays are associated with high density, low powerconsumption, long cycling endurance and fast switching speeds.

In some examples, the resistive memory array to which the input data isassigned is written to represent an operand or a kernel, which may besuited to performing convolutions on input data.

Block 106 comprises buffering output data from at least one processingoperation of the first layer carried out by a resistive memory array.The method further comprises, in block 108, determining whether thebuffered output data exceeds a threshold data amount to carry out atleast one processing operation of the second processing layer; and ifso, in block 110, at least a portion of the buffered output data isassigned to be processed according to a processing operation of a secondprocessing layer, which in some examples may be a processing operationusing at least one resistive memory array.

In this way, the processing of the second processing layer may startwhen the threshold is reached (which may be before the processing of thefirst layer is complete, i.e. the threshold amount may be less than thetotal anticipated output of the first processing layer). In other words,rather than waiting for the first processing layer to be complete, andthen sending the data for processing according to the second processinglayer, at least one processing operation of the first and second layersmay be performed in an overlapping time frame. This method may thereforeprovide a pipeline of data processing in which processing layers arecarried out at least partially concurrently. This may speed processingand may reduce memory capacity specifications for holding the output ofa layer as memory capacity may be reallocated once the output data hasbeen provided to the second layer for processing.

In some examples, the threshold data amount is based on an amount ofdata sufficient to perform at least one processing operation of thesecond processing layer. In some such examples, the threshold data maybe (or may be at least) the minimum amount of data sufficient to performat least one processing operation of the second processing layer. Thismay assist in reducing memory capacity specifications. In some examples,the threshold amount may be related to the data output in a processingcycle of the first layer, i.e. the data may be output in ‘units’, eachunit being output from a particular processing cycle, and the thresholdmay be related to a number of data units.

In some examples, the data may be assigned to different resistive memoryarrays for the processing operation of the first and second processinglayers.

In some examples, the resistive memory arrays which carry out the atleast one processing operation of the second processing layer are withina processing unit comprising a memory (for example, as embedded memorysuch as eDRAM), and buffering the output data comprises buffering theoutput data in the memory of the processing unit to carry out the atleast one processing operation of the second processing layer. In otherwords, the output data may be buffered at a location which is proximateto processing apparatus associated with the second layer (or moregenerally, with the subsequent layer of processing). This buffering maybe a first or a subsequent buffering of the output data.

A method which may for example be used in setting up a processingapparatus to carry out the method of FIG. 1 is now described withreference to FIG. 2. In block 202, a number of resistive memory arraysto be allocated to a processing layer is determined based on therelative processing rates of the layers, wherein the determining is tobalance processing rates of the layers.

In other words, more arrays may be assigned to layers in which theprocessing rate(s) of processing operations are slower than are assignedto layers in which the processing rate(s) are quicker, so as to even outthe processing rates of each layer as a whole by increasing theparallelism within some layers compared to other layers. Thisdetermination may for example be so as to maximise the average usage ofthe arrays in the layers, such that the idle periods of the array(s) isreduced or minimised.

In an example, the second processing layer is associated with at leastone input data buffer in which the output data of the first processinglayer is buffered, and block 204 comprises allocating, by at least oneprocessor, a size of a data buffer based on at least one of thethreshold data amount (for example as discussed in relation to blocks106 and 108 above) and a difference in processing rates (or a differencein processing rates of a processing operation) between the first andsecond layer.

In an example, a processing layer processes the content of the bufferusing a K_(y) array, which is applied to an input data portion instages. This can be visualised as processing input data which fallswithin a moving window, wherein the movement of the window is specifiedin terms of strides and is illustrated with reference to FIG. 3a-c . Inthis example, the input data portion comprises a 6×6 array of valuesnumbered 0 to 35, for example representing a feature map derived from animage, and the operating kernel is a 2×2 operating kernel. The kernelmay first be convolved with the four values from the top left, shown inbold outline in FIG. 3a (values 0, 1, 6 and 7). In this example the‘stride’ is one value in the y direction (one column) and two values inthe x direction (two rows). The row wise shift is applied first. Thus,the next convolution carried out is between the operating kernel and thecentral block of values in the first two columns (values 2, 3, 8 and 9),shown in bold outline in FIG. 3b . The operand is applied as a slidingwindow down the rows, until all of the data blocks of the first twocolumns have undergone convolution. Then the 1-value column-wise shiftis applied, such that the second and third values of the first andsecond rows (values 6, 7, 12 and 13) are processed as shown in boldoutline in FIG. 3c . The processing in this layer may be characterisedas having a stride S_(x)=2, S_(y)=1. The processing rate is determinedby how many convolutions may be carried out in a unit time. Thus, if thekernel is represented by two similarly specified resistive memory arraysrather than one, different data portions may be convolved with each ofthe resistive memory arrays (i.e. two processing operations of the layermay be carried out at once) and the processing rate for that layer maybe doubled.

In this example, it may be noted that each move of the kernel means thatit operates on two new data values (i.e. two data values which were notincluded in the previous convolution). For example, in order to move thekernel from its position in FIG. 3a to FIG. 3b , values 8 and 9 shouldbe received (values 2 and 3 would have been received previously). Thus,in order for this kernel to be used without idle periods, two new datavalues should be received from the previous layer in the time for asingle processing operation in this layer. Therefore, in order tobalance the processing rates, the previous layer may be allotted doublethe number of arrays to this example layer. It may be noted thereforethat stride may be used to quantify a difference in processing rates;and/or that a determination of the resources in a layer may be madebased on the stride(s) of the layer(s).

FIG. 4 is an example of a processing apparatus 400 comprising aplurality of processing units 402, wherein each of the processing units402 comprises a plurality of resistive memory arrays 404, a buffer 406and a control unit 408. Each of the resistive memory arrays 404 is foruse in performing a processing operation in a layer of a multilayerprocessing task. At least one of the arrays 404 is to perform aprocessing operation in a different layer of the multilayer processingtask than the layer of at least one other array. In other words, theprocessing apparatus 400, when in a particular state such that thearrays are written to represent operating kernels, comprises arrays 404which are associated with the operands of multiple layers. In someexamples, the arrays 404 of the processing apparatus 400 may representall, or substantially all, of the convolution layers to be carried outusing the arrays 404.

Each processing unit 402 may comprises a processing ‘tile’, and theremay be at least one such tile on a die or a chip (if there a multipletiles, some components, for example a buffer, may be shared in someexamples). The buffer 406 may comprise an embedded memory, and may be toreceive data for processing by the resistive memory arrays of the sameprocessing unit 402. In some examples, the buffer 406 may be connectedto the resistive memory arrays 404 of the processing unit 402 via a databus which is configured to handle the maximum bandwidth to carry thebuffered data to the arrays 404 within one data operation period (termeda ‘stage’ herein after) of the arrays 404. In some examples, the buffer406 comprises a “first in first out” (FIFO) data buffer, and providesdata storage in a column-wise manner. As data is received, this may bestored in the buffer 406. When the buffer 406 is full, the data may beoverwritten such that new data will overwrite oldest data.

In this example, when the control unit 408 determines that sufficientdata has been received in the buffer 406 to carry out a processing taskusing at least one of the arrays 404, it sends at least a portion of thedata for processing with at least one resistive memory array 404, forexample via a bus. An example of a processing unit 402 is described ingreater detail with reference to FIG. 5 below.

Referring to the example of FIG. 3, assuming that the data values arereceived in order, determining that sufficient data has been received inthe buffer to carry out a processing task would comprises determiningthat data values 0-7 had been received, as the first convolution iscarried out on data values 0, 1, 6 and 7.

In this example, the processing apparatus 400 further comprises acontroller 410 to allocate at least one of resistive memory arraycapacity and memory capacity to each of the layers of the multilayerprocessing task. For example, the controller 410 may carry out theprocess of FIG. 2, or of FIG. 6 described below. The processingapparatus 400 in this example comprises an H-tree configuration, furthercomprises an interconnection link 412 between the processing units 402.In some examples, a different topology, for example a mesh, or a ‘fattree’ topology, may be used.

FIG. 5 shows an example of a processing unit 500, which could forexample provide the processing unit 402 of FIG. 4, and in which likeparts are labelled with like numbers. In this example, the arrays 404are crossbar arrays, each with 128 rows and 128 columns, and four sucharrays 404 are included in each of a plurality of In-situMultiply-Accumulate (IMA) units 502. Each of the arrays 404 isassociated with a Digital to Analogue Converter (DAC) unit 504 and ashift and hold (S+H) unit 506. The IMA units 502 further comprise aninput register IR 508, an Analogue to Digital Converter ADC unit 510, ashift and add (S+A) register 512 and an output register OR 514.

The processing unit 500 further comprises at least one shared outputregister OR 516 which may store an output from a plurality of the IMAunits 502 until all data portions which are to be processed the IMAunits 502 of that processing unit 500 in that layer in a processingcycle are received thereby. The processing unit 500 further comprisesprocessing apparatus which may be used in the conjunction with the IMAunits 502, comprising a shift and add (S+A) unit 518, a max-pool unit520, and a sigmoid unit 522. A bus 526 links the buffer 406, the IMAunits 502 and the other processing apparatus.

In an example of processing using the processing unit 500 for anarbitrary processing layer i, a data input (for example a number ofinput feature maps N_(i), each comprising 16-bit values) may bereceived. Subsequent operations may be carried out in stages with astage time dictated by the slowest stage, which may comprise reading anarray 404, and be on the order of 100 ns. In the first stage, the buffer406 (for example comprising eDRAM) is read to provide a data portion,for example 256 16-bit inputs. These values are sent over the bus 526 tothe IMA unit(s) 502 comprising array(s) 404 allocated to carrying outthe processing of layer i and are recorded in the input register 508. Inthis example, the input register 508 has a maximum capacity of 1 KB andis implemented with SRAM. The bus 526 and the buffer 406 may bespecified such that an entire copy of up to 1 KB of data from buffer 406to the input register 508 is performed within a 100 ns stage. Once theinput values have been copied to the input register 508, the IMA unit502 carries out dot-product operations for the next 16 stages. In thenext 16 stages, the buffer 406 is ready to receive other inputs and mayaddress this data to other IMA unit(s) 502 of the processing unit (e.g.,the control unit 408 may direct data based on a context from which alayer may be identified to IMA unit(s) 502 for that layer).

Returning to the IMA unit 502 to which data has been sent, in thisexample, over the next 16 stages, the IR 508 feeds 1 bit at a time foreach of the 256 input values to the arrays 404. The first 128 bits aresent via the respective DAC units 504 to a first and second array 404,and the next 128 bits are sent to a third and fourth array 404. In thisexample, layer i is performing a convolution with a 4×4 shared kerneland the kernel stride (Sx and Sy) is equal to one.

Layer i performs a dot-product operation with a 4×4×16 matrix, i.e., 256multiply-add operations are carried out. 32 such operations may becarried out in parallel to produce 32 outputs. This may be achieved with256 array rows. Because each of these 32 operations is performed across8 2-bit memristor cells in a row, this may be achieved with 256 arraycolumns. In some examples, this may be the size of a single array, butin other examples, this may be represented by multiple arrays. In thisexample, the 256×256 rows and columns may be represented across the fourarrays 404 of size 128×128 in an IMA unit 502. In this example, the fourarray 404 of single IMA unit 502 may perform the computations of layeri, although arrays from multiple IMA units 502 may carry out theprocessing of layer i.

At the end of each 100 ns stage, the outputs are latched in the Sample &Hold units 506. In the next stage, these outputs are fed to the ADC unit510. The results of the ADC unit 510 are then fed to the shift-and-addregister 512, where the results are merged with the output register 514in the IMA unit 502. The output register 514 in this example is a 128BSRAM structure, although it may have other sizes and/or comprise adifferent memory type in other examples. In this example, the outputregister 514 produces 32 16-bit values over a 16-stage period. In eachstage, the results of the ADC unit 510 are shifted and added to thevalue in the output register 514. Since in this example, the stage is a100 ns stage, this allows 100 ns to update up to 64 16-bit values, whichmay be achieved with four parallel shift-and-add units, which representsa small area overhead.

At the end of stage 19 (to briefly recap, stages 1-18 comprising onestage to receive data, 16 stages to process the data, one stage for‘sample and hold’ operations, and one stage for ‘shift and add’operations, as described above), the output register 514 in the IMA unit502 has its final output value. This is sent over the bus 526 to thecentral output register 516 (via the shift and add unit 518 if theconvolution is spread across multiple IMA units 502). The central outputregister 516 contains the final results for layer i at the end of stage20. Thus, in this example, the processing cycle (i.e. the time for datato be accessed, processed and a result returned) for the example layer icomprises 20 stages. In the meantime, the IMA unit 502 for layer i mayhave already begun processing its next inputs (for example the nextprocessing cycle for layer i), so may be continuously busy in everystage (i.e. processing cycles for layer i may be interleaved, or carriedout at least partially concurrently). In addition, the data output fromlayer i may then be passed for processing in layer i+1 while at leastone processing unit continues to carry out at least one processingoperation of layer i (i.e. at least one processing operation (aprocessing cycle, or a stage thereof) of layer i and at least oneprocessing operation of layer i+1 may be carried out in an overlappingtime frame, or in other words, at least some processing in layer i maybe carried out concurrently with some processing in layer i+1). In otherexamples, if multiple IMA units 502 are used in a processing layer, thenanother shift and add or add to combine results stage may be used tocombine the outputs for the multiple IMA units 502.

In some examples, the output data may be processed by an IMA unit 502 ofthe same processing unit 500, or may be sent to a buffer of anotherprocessing unit 500. In an example, the contents of the central outputregister 516 may be processed in at least some layers by the sigmoidunit 522, for example in a stage 21, which may operate as a smoothingfunction, applying a sigmoid function such as tan h(x) to the output. Instage 22, the sigmoid results may be written to another buffer 406,which may specifically be a buffer 406 associated with array(s) 404which are written with kernels to be applied in the next processinglayer, i+1. In such an example, the processing cycle for layer i maycomprise 22 stages. If this is another IMA unit 502 of the sameprocessing unit 500, this buffer 406 may be the buffer 406 used to storethe inputs for layer i+1. In some examples, the same processing unit 500may be used unless at least one component or class of components thereof(for example the buffer 406, or the IMA units 502) is/are fullyutilised.

The max-pool unit 520 may be used in order to convert multiple valuesinto fewer values. In an example, layer i may output 32 outputs to befed to layer i+1 that performs a max-pool operation on every 2×2 grid oneach filter. The 32 down-sized filters are then fed as input to layeri+2. In this case, in layer i+1, each max-pool operation may comprise afilter which produces four values every 64 stages (16 stage for an IMAunit 502 to complete convolution to generate an output). Hence, amax-pool operation may be performed every 64 stages per filter. Sincethere are 32 such filters generating outputs in parallel, max-poolingfor 32 filters may be performed in parallel every 64 stages. The resultsof the max-pool may be written to a buffer 406 of the processing unit500 used for layer i+2 in stage 27.

Thus it may be noted that it need not be the case that each layer of themultilayer processing utilises resistive memory arrays 404. In somelayers, other processor types may be used to operate on data.

FIG. 6 is an example of a method, which may in some examples be a methodfor use in setting up a processing apparatus such as the processingapparatus 400 of FIG. 4.

Block 602 comprises determining a processing pipeline for multiplelayers of processing using resistive memory arrays, wherein for eachlayer after a first layer, processing is carried out on the output of apreceding layer; and wherein the processing for at least two layers isto be carried out at least partially concurrently.

Block 604 comprises determining an allocation of processing resourcesfor the processing pipeline, the allocation comprising determining adistribution of resistive memory arrays between the layers so as tobalance an output bit rate of bits by processing of a previous layer anda processing bit rate in processing of a subsequent layer.

As has been discussed above with reference to FIGS. 3a-c , processing ofa subsequent layer may, in some examples described herein, be commencedonce sufficient bits have been received from a previous layer.Considering the example of FIG. 3 (but assuming a stride of 1 ratherthan 2), this means that bits 0-7 are received from a previous layerbefore the next layer processing commences. When a previous layer i−1produces output data value 8, it may be placed in the input buffer forlayer i. At this point, value 0 is no longer useful and can be removedfrom the input buffer. Thus, every new output produced by layer i−1allows layer i to advance the kernel by one stage and perform a newoperation of its own. In this example, a set of inputs (which maycomprise feature maps) is fed to N_(of) convolutional kernels to produceN_(of) output feature maps. Each of these kernels may a different columnin a resistive memory array may operate on a set of inputs in parallel.

As has been mentioned above in relation to FIGS. 2 and 3, if aK_(x)×K_(y) kernel may be moved by strides S_(x) and/or S_(y) afterevery stage. If for example S_(x)=2 and S_(y)=1, the previous layer i−1has to produce two values before layer i can perform its next processingoperation. More generally, the number of output values produced by layeri−1 in order for the level i processing operation to be performed is afunction of stride values associated with level i. This could cause anunbalanced pipeline where the arrays of layer i−1 are busy in everycycle, while the arrays of layer i may be idle in some cycles, forexample alternating between being busy and idle in alternate cycles. Tobalance the pipeline, the resources allocated to layer i−1 may bedoubled by replicating the synaptic weights representing the kernel(s)for layer i−1 in a different array so that two different input vectorscan be processed in parallel to produce two output values in one cycle.

FIG. 7 comprises a method including block 602 of FIG. 6. In thisexample, blocks 702 and 704 are an example of determining a distributionof resistive memory arrays as described in block 604 by allocating asynaptic weight memory capacity to each of the layers, the memorycapacity being for storing synaptic weights. This may compriseallocating the total bit capacity of all arrays to be used in processingthat layer (the elements of these arrays represent the ‘weights’ whichare to be applied to the input values, termed synaptic weights in thefield of neural networks, by analogy with brain synapses). In block 702,the memory capacity for a final layer is determined according to thenumber of data potions to be processed (for example, a number of inputfeature maps for that layer N_(if)), the number of data portions to beoutput (for example, a number of output feature maps for that layerN_(of)), and the size of an operand to operate on the data portions (forexample, the kernel size K_(x)×K_(y), where K_(y) and K_(x) are thenumber of columns and rows in the kernel).

For example, if the last layer is expected to produce outputs in everycycle, it may be allocated with memory to storeK_(x)×K_(y)×N_(if)×N_(of) synaptic weights.

Block 704 comprises determining the synaptic weight memory capacity tobe allocated for at least one preceding layer. This may be determinedaccording to the number of data potions to be processed (N), the numberof data portions to be output N_(of), the size of an operand to operateon the data portions (for example, the kernel size K_(x)×K_(y)) and theoutput bit rate of processing operations carried out in the processinglayer (for example, determined based on the stride, such that the memoryallocation increases when the stride is higher, or conversely whenoutput bit rate of the processing operations is lower).

In an example, the synaptic weight memory allocated for layer i may beK_(xi)×K_(yi)×N_(ifi)×N_(ofi)×S_(xi+1)×S_(yi+1). This therefore allowsthe weights for layer i to be stored multiple times if S_(xi+1) orS_(yi+1) is greater than one

In some examples, if the aggregate storage specification exceeds theavailable storage on a chip by a factor (for example by a factor of two)then the storage allocated to every layer except the last may be reducedby the factor. In such an example, the pipeline remains balanced andmost arrays may be busy in every cycle; but the very last layer mayperform an operation and produces a result in some cycles and not others(if the factor is a factor of two, a result may be produced in everyalternate cycle).

Determining the synaptic weight specification of each layer may thenlead to an allocation of arrays to each layer, as the synaptic weightsmay be represented by the elements of the arrays.

Block 706 comprises allocating a buffer memory capacity to each of thelayers, the buffer memory capacity being to store input data forprocessing in the layer, wherein the buffer memory capacity isdetermined based on the number of data potions (which may for examplecomprise feature maps) to be processed (NO) in parallel (i.e. how manyprocessing operations are carried out at one time), the number of rowsof an input feature map to be processed with each array, and the size ofan operand to operate on the data portions (for example, the kernel sizeK_(x)×K_(y)).

For example, a buffer may be allocated to comprise storage space for atleast: ((N_(x)×(K_(y)−1))+K_(x))×N_(if), where N_(x) is the number ofrows in the input feature map, K_(y) and K_(x) are the number of columnsand rows in the kernel, and N_(if) is the number of input feature mapsfor the layer.

It may be noted that, if the entire layer was to be processed and theoutput feature maps stored, this would suggest a buffering capacity ofN_(x)×N_(y)×N_(if) from layer i−1 before starting layer i. Thus, bystarting one layer while a previous layer continues, this may reduce thespecified buffering capacity by around N_(y)/K_(y).

In the examples above, the control units 408 of the processing units 402may route the data between layers. However, in other examples, thecontroller 410 may route the data, and/or there may be a central bufferas well as or in place of the buffers 406 of the processing units 402.In some examples, data portions which are addressed in a particularlayer are kept in a destination register (one of which may be providedfor each layer) which is accessible to the controller 410 and/or thecontrol units 408.

FIG. 8 shows an example of a data packet 800 which may be received by aprocessing unit 402, 500. The data packet 800 in this example comprisesrouting information 802, which comprises network metadata such as adestination identifier identifying a processing unit 402, 500, VirtualCircuit information 804, a layer index 806, an indication of the numberof data pieces 808 (which in this example is two), and at least one datapiece 810. In this example each data piece 810 comprise an input index810 a and a plurality of data bits 810 b. The number of data bits may bethe same as the number of input rows of an array 404.

On receipt of such a data packet 800, in one example, processing unit402, 500 may operate according to the following data flow:

An incoming data packet 800 may be unpacked, for example in a depackunit of a control unit 408 of a processing unit 402. The layer index 806may provide an index to a mapping table which is accessed by the controlunit 408 to identify the IMA unit 502 and/or arrays 404 by which eachdata piece 810 is to be processed. The input index 810 a of a data piece810 may be used in the event that one layer has multiple data pieces.

Examples in the present disclosure can be provided as methods, systemsor machine readable instructions, such as any combination of software,hardware, firmware or the like. Such machine readable instructions maybe included on a computer readable storage medium (including but is notlimited to disc storage, CD-ROM, optical storage, etc.) having computerreadable program codes therein or thereon.

The present disclosure is described with reference to flow charts and/orblock diagrams of the method, devices and systems according to examplesof the present disclosure. Although the flow diagrams described aboveshow a specific order of execution, the order of execution may differfrom that which is depicted. Blocks described in relation to one flowchart may be combined with those of another flow chart. It shall beunderstood that each flow and/or block in the flow charts and/or blockdiagrams, as well as combinations of the flows and/or diagrams in theflow charts and/or block diagrams can be realized by machine readableinstructions.

The machine readable instructions may, for example, be executed by ageneral purpose computer, a special purpose computer, an embeddedprocessor or processors of other programmable data processing devices torealize the functions described in the description and diagrams (forexample, the controllers 410, the control unit 408, the max-pool unit520, the sigmoid unit 522 and the like). In particular, a processor orprocessing apparatus may execute the machine readable instructions. Thusfunctional modules of the apparatus and devices may be implemented by aprocessor executing machine readable instructions stored in a memory, ora processor operating in accordance with instructions embedded in logiccircuitry. The term ‘processor’ is to be interpreted broadly to includea CPU, processing unit, ASIC, logic unit, or programmable gate arrayetc. The methods and functional modules may all be performed by a singleprocessor or divided amongst several processors.

Such machine readable instructions may also be stored in a computerreadable that can guide the computer or other programmable dataprocessing devices to operate in a specific mode.

Such machine readable instructions may also be loaded onto a computer orother programmable data processing devices, so that the computer orother programmable data processing devices perform a series ofoperations to produce computer-implemented processing, thus theinstructions executed on the computer or other programmable devicesrealize functions specified by flow(s) in the flow charts and/orblock(s) in the block diagrams.

Further, the teachings herein may be implemented in the form of acomputer software product, the computer software product being stored ina storage medium and comprising a plurality of instructions for making acomputer device implement the methods recited in the examples of thepresent disclosure.

While the method, apparatus and related aspects have been described withreference to certain examples, various modifications, changes,omissions, and substitutions can be made without departing from thespirit of the present disclosure. It is intended, therefore, that themethod, apparatus and related aspects be limited only by the scope ofthe following claims and their equivalents. It should be noted that theabove-mentioned examples illustrate rather than limit what is describedherein, and that those skilled in the art will be able to design manyalternative implementations without departing from the scope of theappended claims. Features described in relation to one example may becombined with features of another example.

The word “comprising” does not exclude the presence of elements otherthan those listed in a claim, “a” or “an” does not exclude a plurality,and a single processor or other unit may fulfil the functions of severalunits recited in the claims.

The features of any dependent claim may be combined with the features ofany of the independent claims or other dependent claims.

1. A method comprising: receiving, in a memory, input data to beprocessed in a first and a second processing layer, wherein, in thesecond processing layer, a processing operation is carried out on anoutput of a processing operation of the first processing layer, and aprocessing operation of the first processing layer is carried out usingat least one resistive memory array; assigning the input data to beprocessed according to at least one processing operation of the firstprocessing layer, buffering output data from at least one processingoperation of the first processing layer, determining whether thebuffered output data exceeds a threshold data amount to carry out atleast one processing operation of the second processing layer; and, whenit is determined that the buffered output data exceeds the thresholddata amount; assigning at least a portion of the buffered output data tobe processed according to at least one processing operation of a secondprocessing layer.
 2. The method of claim 1 in which the threshold dataamount is based on an amount of data sufficient to perform at least oneprocessing operation of the second processing layer.
 3. The method ofclaim 1 further comprising performing at least one processing operationof the first and second processing layers in an overlapping time frame.4. The method of claim 1 further comprising assigning input data todifferent resistive memory arrays for the processing operation of thefirst and second processing layers.
 5. The method of claim 1, in whichat least one processing operation of the second processing layer iscarried out using a resistive memory array, and the resistive memoryarray is within a processing unit comprising a memory, and whereinbuffering the output data comprises buffering the output data in thememory of the processing unit to carry out the at least one processingoperation of the second processing layer.
 6. The method of claim 1 inwhich each layer is associated with a processing rate, the methodcomprising determining, by at least one processor, a number of resistivememory arrays to be allocated to a processing layer based on relativeprocessing rates of the layers, wherein the determining is to balanceprocessing rates of the layers.
 7. The method of claim 1 in which theoutput data of the first processing layer is buffered in at least oneinput data buffer of the second processing layer, the method comprisingallocating, by at least one processor, a size of a data buffer based onat least one of the threshold data amount; a difference in processingrates between the first and second processing layer; and a difference inprocessing rates of a processing operation of the first and a processingoperation of the second processing layer.
 8. A processing unitcomprising a plurality of resistive memory arrays, a buffer and acontrol unit, wherein each of the resistive memory arrays is for use inperforming a processing operation in a layer of a multilayer processingtask, wherein: the buffer is to receive input data; and the control unitof the processing unit is to: determine that sufficient data has beenreceived in the buffer to carry out a processing task using at least oneof the resistive memory arrays; and send at least a portion of the datafor processing with at least one resistive memory array.
 9. Theprocessing unit of claim 8 further comprising at least one outputregister to store an output from a plurality of resistive memory arraysuntil all data portions which are to be processed by resistive memoryarrays of that processing unit in a processing cycle of a layer arereceived thereby.
 10. The processing unit of claim 19 in which at leastone array is to perform a processing operation in a first layer of themultilayer processing task and at least one array is to perform aprocessing operation in a second layer of the multilayer processingtask.
 11. The processing unit of claim 8 further comprising at least oneof a shift and add unit, a max-pool unit, and a sigmoid unit.
 12. Theprocessing unit of claim 8 in which the control unit comprises aplurality of in-situ multiply-accumulate units each comprising aplurality of resistive memory arrays associated with at least one shiftand hold unit.
 13. A method comprising: determining a processingpipeline for multiple layers of processing using resistive memoryarrays, wherein for each layer after a first layer, processing iscarried out on an output of a preceding layer; and wherein processingfor at least two layers is to be carried out at least partiallyconcurrently; and determining an allocation of processing resources forthe processing pipeline, the allocation comprising determining adistribution of resistive memory arrays between at least two of thelayers so as to balance an output bit rate of bits by processing of aprevious layer and a processing bit rate in processing of a subsequentlayer.
 14. The method of claim 13 in which determining an allocation ofprocessing resources comprises determining a synaptic weight memorycapacity for each of the layers, the synaptic weight memory capacitybeing for storing synaptic weights, wherein the synaptic weight memorycapacity for a final layer is determined according to a number of datapotions to be processed, a number of data portions to be output, and asize of an operand to operate on the data portions; and wherein thesynaptic weight memory capacity for at least one preceding layer isdetermined according to the number of data potions to be processed, anumber of data portions to be output, and the size of an operand tooperate on the data portions and an output bit rate of processingcarried out in the layer.
 15. The method of claim 13 further comprisingallocating a buffer memory capacity to each of the layers, the buffermemory capacity being to store input data for processing in the layer,wherein the buffer memory capacity is determined based on the number ofdata potions to be processed, a number of parallel operations to becarried out on the data portions, and the size of an operand to operateon the data portions.